An alleged die-layout reconstruction of Apple’s A20 Pro offers a closer look at how the company’s next-generation chip could be organized internally. The analysis points to a 2+4 CPU configuration alongside a seven-core GPU, with the layout inferred largely from the chip’s solder-joint pattern.
The reconstruction comes from Weibo user White rice fried white rice, who analyzed the package connections and compared them with previous Apple chip layouts. The findings remain unofficial, but the approach provides a useful look at how chip architecture can sometimes be inferred before Apple publishes detailed specifications.
Reading the layout from the solder joints
The analysis starts with the A20 Pro’s solder-joint diagram. These tiny connections sit between the silicon package and the rest of the device, but their positions also hint at how different parts of the chip are arranged.
The researcher first identified the LPDDR memory interface on the far right of the package. By overlaying the die and solder-joint diagrams, diagonal and vertical patterns in the connections helped establish the approximate boundaries of internal blocks.
That outline was then compared with previous Apple die layouts. Based on the positioning of those blocks, the upper portion was attributed to the GPU, while the central area was identified as the CPU section.
The CPU reconstruction suggests two performance cores and four efficiency cores, giving the A20 Pro a 2+4 configuration.
Seven GPU cores fit the available space
The GPU portion was a harder puzzle. According to the analysis, more than ten possible arrangements were tested using six, seven, and eight-core configurations.
The seven-core arrangement reportedly produced the most convincing match with the available solder-joint positions and the inferred boundaries of the GPU area. The resulting reconstruction labels seven individual GPU blocks across the upper section of the die.
That does not confirm seven GPU cores. It means the proposed arrangement appears to fit the physical evidence better than the alternatives examined.
The same reconstruction identifies multiple L2 cache blocks around the CPU. The smaller efficiency-core cluster is alleged to receive an increase from 6MB on the A19 Pro to 8MB, while the larger performance-core cluster could retain its 16MB L2 cache.
The chip’s system-level cache, or SLC, remains unknown. The source argues that Apple is unlikely to reduce it, particularly if the A20 Pro introduces a new ISP and Neural Engine that could place greater demands on shared cache capacity.
Why the package can reveal so much
Solder joints do not directly label a CPU core or cache block. Instead, their geometry can expose the physical constraints that the silicon beneath must follow.
Apple’s previous chip layouts provide another reference point. By comparing recurring structures, interface positions, and approximate block proportions across generations, researchers can make educated estimates of where CPU, GPU, cache, and memory-related circuitry are located.
That makes this a physical reconstruction rather than a specification leak.
The distinction matters. A seven-core GPU cannot be confirmed simply because one arrangement fits a solder map, and estimated cache sizes are similarly dependent on how accurately the underlying die boundaries have been interpreted.
Still, the proposed A20 Pro layout gives a more concrete picture than a conventional specification rumor. If the reconstruction is broadly correct, Apple could be moving to a 2+4 CPU design with a seven-core GPU while expanding the efficiency-core L2 cache to 8MB.
The bigger question is how these architectural changes translate into performance once the A20 Pro reaches finished hardware. Until then, the solder pattern offers clues about what Apple built, but not yet how fast it will run.
