TSMC is preparing to move its A16 process into mass production in the fourth quarter of 2026, according to a report ChosunBiz published on August 20. The 1.6nm-class technology targets AI and high-performance computing chips, where power delivery and signal routing have become increasingly difficult at advanced nodes.
The timeline is consistent with TSMC’s own guidance. The company previously said A16 volume production was on track for the second half of 2026, making a Q4 ramp a more specific target rather than a major change to its published roadmap.
A16 focuses on power delivery as much as transistor scaling
A16 is built around TSMC’s Super Power Rail, or SPR, technology. Unlike conventional designs where much of the power-distribution network competes with signal wiring on the front side of the chip, SPR moves power delivery to the backside.
That frees more front-side routing resources for signals while allowing the power network to better handle the demands of dense HPC designs. TSMC positions A16 specifically for products with complex signal paths and demanding power-delivery requirements.
Compared with the N2P process, TSMC says A16 can deliver an 8% to 10% performance increase at the same power, or reduce power consumption by 15% to 20% at the same performance. The company also cites an additional 7% to 10% chip-density improvement in its earlier process disclosures.
Those figures are process-level targets, not benchmarks from finished consumer products. Actual gains will depend on chip architecture, design rules, workloads, and how aggressively manufacturers use the additional density and power headroom.
The timing matters for AI chips
TSMC’s A16 push comes as advanced-node demand is increasingly being shaped by AI accelerators and other HPC silicon. The company said its N2 process entered high-volume manufacturing in the fourth quarter of 2025, with strong demand from both smartphone and HPC/AI applications.
A16 is a different proposition from simply shrinking a smartphone processor. Its backside power architecture is particularly useful when a chip has large amounts of data moving through tightly packed logic while also requiring substantial power delivery.
That could make the process attractive for future AI accelerators, custom data-center silicon and other large compute designs. Consumer processors may benefit later, but A16’s initial positioning is clearly weighted toward HPC.
The broader foundry race also makes the Q4 target significant. Samsung is continuing to develop its 2nm-class processes, while Intel is advancing its 18A family and preparing 14A for later production. A16’s value will ultimately depend less on having a smaller number in its name and more on whether TSMC can deliver competitive yields, capacity, and customer products at scale.
ChosunBiz’s report provides the latest Q4 production timeline, while TSMC’s statements set the broader second-half-2026 target. The next question is how quickly A16-based products move from wafer production to commercially available chips — and which major AI customers are first to take advantage of its backside power architecture.
